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1 ? caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2007, 2008, 2009. all rights reserved all other trademarks mentioned are the property of their respective owners.. isl89400, isl89401 100v, 1.25a peak, high frequency half-bridge drivers the isl89400, isl89401 are 100v, high frequency, half-bridge n-channel power mosfet driver ics. they are based on the popular hip2100, hip2101 half-bridge drivers, but offer several performance improvements. the isl89400 has additional input hysteresis for superior operation in noisy environments and the inputs of the isl89401 (like those of the isl89400) can now safely swing to the v dd supply rail. finally, both parts are available in a very compact 9 ld dfn package and an 8 ld soic to minimize the required pcb footprint. features ? drives n-channel mosfet half-bridge ? space saving dfn package ? dfn package compliant with 100v conductor spacing guidelines per ipc-2221 ? pb-free (rohs compliant) ? bootstrap supply max voltage to 114vdc ? on-chip 1 bootstrap diode ? fast propagation times for multi-mhz circuits ? drives 1nf load with typical rise/fall times of 16ns ? cmos compatible input thresholds (isl89400) ? 3.3v/ttl compatible input thresholds (isl89401) ? independent inputs provide flexibility ? no start-up problems ? outputs unaffected by supply glitches, hs ringing below ground or hs slewing at high dv/dt ? low power consumption ? wide supply voltage range (9v to 14v) ? supply undervoltage protection ?4.0 typical output pull-up/pull-down resistance applications ? telecom half-bridge converters ? telecom full-bridge converters ? two-switch forward converters ? active-clamp forward converters ? class-d audio amplifiers ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # isl89400ar3z* 9400 -40 to +125 9 ld 3x3 dfn l9.3x3 isl89401ar3z* 9401 -40 to +125 9 ld 3x3 dfn l9.3x3 ISL89400ABZ** 89400 abz -40 to +125 8 ld soic m8.15 isl89401abz** 89401 abz -40 to +125 8 ld soic m8.15 *add ?-t? suffix for tape and reel. **add ?-tk? suffix for tape and reel. please refer to tb347 for details on reel specifications. note: these intersil pb-free pl astic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. pinouts isl89400, isl89401 (8 ld soic) top view isl89400, isl89401 (9 ld dfn) top view 5 6 8 7 4 3 2 1 v dd hb ho hs lo li hi v ss v dd hb ho hs lo v s s li hi nc epad 2 3 1 4 8 7 6 9 5 note: epad = exposed pad. data sheet august 11, 2009 fn6614.2
2 fn6614.2 august 11, 2009 application block diagram functional block diagram secondary circuit +100v control controller pwm li hi ho lo v dd hs hb +12v v ss reference and isolation drive lo drive hi isl89400 isl89401 undervoltage v dd hi li v ss driver driver hb ho hs lo level shift undervoltage epad (dfn package only) isl89401 isl89401 *epad = exposed pad. the epad is electrically isolated from all other pins. for best thermal performance, connect the epad to the pcb power ground plane. isl89400, isl89401
3 fn6614.2 august 11, 2009 secondary isolation pwm +48v +12v circuit figure 1. two-switch forward converter isl89400 isl89401 secondary circuit isolation pwm +48v +12v figure 2. forward converter with an active-clamp isl89400 isl89401 isl89400, isl89401
4 fn6614.2 august 11, 2009 absolute maximum rati ngs thermal information supply voltage, v dd, v hb - v hs (notes 1, 2) . . . . . . . -0.3v to 18v li and hi voltages (note 2) . . . . . . . . . . . . . . . -0.3v to v dd + 0.3v voltage on lo (note 2) . . . . . . . . . . . . . . . . . . -0.3v to v dd + 0.3v voltage on ho (note 2) . . . . . . . . . . . . . . v hs - 0.3v to v hb + 0.3v voltage on hs (continuous) (note 2) . . . . . . . . . . . . . . -1v to 110v voltage on hb (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118v average current in v dd to hb diode . . . . . . . . . . . . . . . . . . 100ma maximum recommended operating conditions supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9v to 14v voltage on hs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to 100v voltage on hs . . . . . . . . . . . . . . .(repetitive transient) -5v to 105v voltage on hb . . v hs + 8v to v hs + 14v and v dd - 1v to v dd + 100v hs slew rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50v/ns thermal resistance (typical) ja (c/w) jc (c/w) 9 ld dfn (notes 3, 5) . . . . . . . . . . . . . 55 7.5 8 ld soic (note 4) . . . . . . . . . . . . . . . 115 n/a max power dissipation at +25c in free air (notes 3, 5) . . . . . 2.27w storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c junction temperature range. . . . . . . . . . . . . . . . . .-55c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. the isl89400 and isl89401 are capable of derated operation at suppl y voltages exceeding 14v. figure 22 shows the high-side vo ltage derating curve for this mode of operation. 2. all voltages referenced to v ss , unless otherwise specified. 3. ja is measured in free air with the component mounted on a high ef fective thermal conductivity test board with ?direct attach? fe atures. 4. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 5. for jc, the ?case temp? is measured at the center of the exposed metal pad on the package underside. see tech brief tb379 for details. electrical specifications v dd = v hb = 12v, v ss = v hs = 0v, no load on lo or ho, unless otherwi se specified. parameters with min and/or max limits are 100% tested at +25c, unless other wise specified. temperat ure limits established by characterization and are not production tested. parameters symbol test conditions t j = +25c t j = -40c to +125c units min typ max min max supply currents v dd quiescent current i dd isl89400; li = hi = 0v - 0.1 0.25 - 0.3 ma v dd quiescent current i dd isl89401; li = hi = 0v - 0.3 0.45 - 0.55 ma v dd operating current i ddo isl89400; f = 500khz - 1.6 2.2 - 2.7 ma v dd operating current i ddo isl89401; f = 500khz - 1.9 2.5 - 3 ma total hb quiescent current i hb li = hi = 0v - 0.1 0.15 - 0.2 ma total hb operating current i hbo f = 500khz - 2.0 2.5 - 3 ma hb to v ss current, quiescent i hbs li = hi = 0v; v hb = v hs = 114v - 0.05 1 - 10 a hb to v ss current, operating i hbso f = 500khz; v hb = v hs = 114v - 0.9 - - - ma input pins low level input voltage threshold v il isl89400 3.7 4.4 - 2.7 - v low level input voltage threshold v il isl89401 1.4 1.8 - 1.2 - v high level input voltage threshold v ih isl89400 - 6.6 7.4 - 8.4 v high level input voltage threshold v ih isl89401 - 1.8 2.2 - 2.4 v input voltage hysteresis v ihys isl89400 - 2.2 - - - v input pull-down resistance r i - 210 - 100 500 k under voltage protection v dd rising threshold v ddr 6.8 7.3 7.8 6.5 8.1 v v dd threshold hysteresis v ddh -0.6- - - v hb rising threshold v hbr 6.2 6.9 7.5 5.9 7.8 v isl89400, isl89401
5 fn6614.2 august 11, 2009 hb threshold hysteresis v hbh -0.6- - - v boot strap diode low current forward voltage v dl i vdd-hb = 100a - 0.5 0.6 - 0.7 v high current forward voltage v dh i vdd-hb = 100ma - 0.7 0.9 - 1 v dynamic resistance r d i vdd-hb = 100ma - 0.8 1 - 1.5 lo gate driver low level output voltage v oll i lo = 100ma - 0.4 0.5 - 0.7 v high level output voltage v ohl i lo = -100ma, v ohl = v dd - v lo - 0.4 0.5 - 0.7 v peak pull-up current i ohl v lo = 0v - 1.25 - - - a peak pull-down current i oll v lo = 12v - 1.25 - - - a ho gate driver low level output voltage v olh i ho = 100ma - 0.4 0.5 - 0.7 v high level output voltage v ohh i ho = -100ma, v ohh = v hb - v ho - 0.4 0.5 - 0.7 v peak pull-up current i ohh v ho = 0v - 1.25 - - - a peak pull-down current i olh v ho = 12v - 1.25 - - - a electrical specifications v dd = v hb = 12v, v ss = v hs = 0v, no load on lo or ho, unless otherwi se specified. parameters with min and/or max limits are 100% tested at +25c, unless other wise specified. temperat ure limits established by characterization and are not production tested. (continued) parameters symbol test conditions t j = +25c t j = -40c to +125c units min typ max min max switching specifications v dd = v hb = 12v, v ss = v hs = 0v, no load on lo or ho, unless otherwise specified parameters symbol test conditions t j = +25c t j = -40c to +125c units min typ max min max lower turn-off propag ation delay (li fallin g to lo falling) t lphl - 34 50 - 60 ns upper turn-off propagation delay (hi falling to ho falling) t hphl - 31 50 - 60 ns lower turn-on propagation dela y (li rising to lo rising) t lplh - 39 50 - 60 ns upper turn-on propagation delay (hi rising to ho rising) t hplh - 39 50 - 60 ns delay matching: upper turn-off to lower turn-on t mon 1 8 - - 16 ns delay matching: lower turn-off to upper turn-on t moff 1 6 - - 16 ns either output rise/fall time (10% to 90%/90% to 10%) t rc, t fc c l = 1nf - 16 - - - ns either output rise/fall time (3v to 9v/9v to 3v) t r, t f c l = 0.1f - 0.8 1.0 - 1.2 s minimum input pulse width that changes the output t pw - - - - 50 ns bootstrap diode turn-on or turn-off time t bs -10- - - ns isl89400, isl89401
6 fn6614.2 august 11, 2009 timing diagrams pin descriptions symbol description v dd positive supply to lower gate driver. bypass this pin to v ss . hb high-side bootstrap supply. external bootstrap capacitor is re quired. connect positive side of bootstrap capacitor to this pi n. bootstrap diode is on-chip. ho high-side output. connect to gate of high-side power mosfet. hs high-side source connection. connect to s ource of high-side power mosfet. connect negat ive side of bootstrap capacitor to thi s pin. hi high-side input. li low-side input. v ss chip negative supply, which will generally be ground. lo low-side output. connect to gate of low-side power mosfet. nc no connect. epad exposed pad. connect to ground or float. the epad is electrically isolated from all other pins. figure 3. propagation delays figure 4. delay matching t hplh , t lplh t hphl , t lphl hi , li ho , lo t mon t moff li hi lo ho typical performance curves figure 5. isl89400 i dd operating current vs frequency figure 6. isl89401 i dd operating current vs frequency 10k 100k 0.1 1.0 10.0 frequency (hz) i ddo (ma) 1m t = -40c t = +25c t = +150c t = +125c 10k 100k 0.1 1.0 10.0 frequency (hz) i ddo (ma) 1m t = -40c t = +25c t = +125c t = +150c isl89400, isl89401
7 fn6614.2 august 11, 2009 figure 7. i hb operating current vs frequency figure 8. i hbs operating current vs frequency figure 9. high level output voltage vs tempe rature figure 10. low level output voltage vs temperature figure 11. undervoltage lockout threshold vs temperature figure 12. undervoltage lockout hysteresis vs temperature typical performance curves (continued) 10k 100k 1m 0.01 0.10 1.00 10.00 frequency (hz) i hbo (ma) t = -40c t = +25c t = +150c t = +125c 10k 100k 1m 0.01 0.10 1.00 10.00 frequency (hz) i hbo (ma) t = +150c t = +125c t = -40c t = +25c -50 0 50 100 150 150 200 250 300 350 400 450 500 temperature (c) v oll , v olh (mv) v dd = v hb = 12v v dd = v hb = 14v v dd = v hb = 9v -50 0 50 100 150 150 200 250 300 350 400 450 temperature (c) v oll , v olh (mv) v dd = v hb = 9v v dd = v hb = 12v v dd = v hb = 14v -50 0 50 100 150 6.8 7.0 7.2 7.4 7.6 v ddr v hbr temperature (c) v ddr , v hbr (v) -50 0 50 100 150 0.40 0.45 0.50 0.55 0.60 v ddh v hbh temperature (c) v ddh , v hbh (v) isl89400, isl89401
8 fn6614.2 august 11, 2009 figure 13. isl89400 propagation delays vs temperature figure 14. isl89401 propagation delays vs temperature figure 15. isl89400 delay matching vs temperat ure figure 16. isl89401 delay matching vs temperature figure 17. peak pull-up current vs output volt age figure 18. peak pull-down current vs output voltage typical performance curves (continued) -50 0 50 100 150 20 25 30 35 40 45 50 55 t lplh temperature (c) t lplh , t lphl , t hplh , t hphl (ns) t lphl t hplh t hphl -50 0 50 100 150 20 25 30 35 40 45 50 55 temperature (c) t lplh , t lphl , t hplh , t hphl (ns) t lplh t lphl t hplh t hphl -50 0 50 100 150 3 4 5 6 7 8 9 10 t mon t moff temperature (c) t mon , t moff (ns) -50 0 50 100 150 2 3 4 5 6 7 8 9 10 temperature (c) t mon , t moff (ns) t mon t moff 0681012 0 0.25 0.50 0.75 1.00 1.25 v lo , v ho (v) i ohl , i ohh (a) 24 0 4 6 8 10 12 0 0.25 0.50 0.75 1.00 1.25 v lo , v ho (v) i oll , i olh (a) 2 isl89400, isl89401
9 fn6614.2 august 11, 2009 figure 19. isl89400 quiescent current vs voltage figure 20. isl89401 quiescent current vs voltage figure 21. bootstrap diode i-v characteristics figure 22. v hs voltage vs v dd voltage typical performance curves (continued) 0 5 10 15 20 0 20 40 60 80 100 120 140 160 180 200 220 240 260 v dd , v hb (v) i dd , i hb (a) i hb i dd 0 5 10 15 20 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 v dd , v hb (v) i dd , i hb (a) i hb i dd 0.3 0.4 0.5 0.6 0.7 0.8 1 . 10 -3 0.01 0.10 1.00 forward voltage (v) forward current (a) 1 . 10 -4 1 . 10 -5 1 . 10 -6 12 13 14 15 16 0 20 40 60 80 100 120 v hs to v ss voltage (v) v d d t o v s s v o l t a g e ( v ) isl89400, isl89401
10 fn6614.2 august 11, 2009 isl89400, isl89401 small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 8 0 8 - rev. 1 6/05
11 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6614.2 august 11, 2009 isl89400, isl89401 dual flat no-lead plastic package (dfn) // nx (b) section "c-c" for odd terminal/side e cc 4 c l terminal tip (a1) bottom view a 5 area index c c 0.10 0.08 side view 0.15 2x e a b c 0.15 d top view cb 2x 5 7 area index nx l e2 e2/2 ref. e n (nd-1)xe (datum a) (datum b) 4 0.10 7 6 d2 b a c n-1 12 plane seating c a a3 nx b d2/2 nx k 8 l m l9.3x3 9 lead dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a3 0.20 ref - b 0.20 0.25 0.30 4, 7 d 3.00 bsc - d2 1.85 2.00 2.10 6, 7 e 3.00 bsc - e2 0.80 0.95 1.05 6, 7 e 0.50 bsc - k0.60 - - - l 0.25 0.35 0.45 7 n92 rev. 0 3/06 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. all dimensions are in millim eters. angles are in degrees. 4. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 6. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 7. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 8. compliant to jedec mo-229-weed-3 except for dimensions e2 & d2.

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